FXA: Executing Instructions in Front-End for Energy Efficiency

FXA: Executing Instructions in Front-End for Energy Efficiency

Front-End Policies for Improved Issue Efficiency in SMT Processors

The performance and power optimization of dynamic superscalar microprocessors requires striking a careful balance between exploiting parallelism and hardware simplification. Hardware structures which are needlessly complex may exacerbate critical timing paths and dissipate extra power. One such structure requiring careful design is the issue queue. In a Simultaneous Multi-Threading (SMT) proces...

Energy End-Use Efficiency

Increasing energy end-use efficiency—technologically providing more desired service per unit of delivered energy consumed—is generally the largest, least expensive, most benign, most quickly deployable, least visible, least understood, and most neglected way to provide energy services. The 46% drop in U.S. energy intensity (primary energy consumption per dollar of real GDP) during 1975–2005 rep...

Super efficiency model in front of MPSS

By using the Double Frontiers Criteria, Hurwicz succeeded to achieve The Most Productive Scale Size of decision making units. This Double frontiers criteria was achieved by using two models of “CCR” in optimistic viewpoint in input form and the “CCR” model in pessimistic viewpoint in input form. In this paper, we intend to find a criteria for Double frontiers of super efficiency by using two mo...

VLIW-Based Processor for Executing Multi-Scalar/Vector Instructions

This paper proposes new processor architecture for data-parallel applications based on the combination of VLIW and vector processing paradigms. It uses VLIW architecture for processing multiple independent scalar instructions concurrently on parallel execution units. Data parallelism is expressed by vector ISA and processed on the same parallel execution units of the VLIW architecture. The prop...